Conventional semiconductor manufacturing techniques include the deposition of a dielectric layer on a feature layer whereupon the dielectric layer has an initially non-planarized surface whose topography largely matches that of its underlying feature layer and which may also have surface irregularities due to manufacturing limitations.
To achieve high feature density, a dielectric layer has to be planarized to a high degree of global planarity hitherto achieved using chemical mechanical polishing (CMP) technology, however, this suffers from several drawbacks including inter alia a CMP machine requires a large cleanroom floor space and consumes large quantities of costly consumables; operational difficulties due to abrasion being affected by several factors including die location, spacing between features, pad condition and slurry distribution.
In an article entitled "Grazing Angle Laser Planarization Process for Multi-Level Thin Film Structure" by Patel et al, IBM Microelectronics Division, SPIE ISHM '95 Proceedings, pages 31-35, there has been proposed laser assisted planarization by means of a laser beam intensively ablating local protrusions at a low incidence angle.